This application is related to the field of semiconductor devices and, more particularly, to capacitor structures in integrated circuits.
In integrated circuit design there are many applications of high-performance, on-chip capacitors. These applications include dynamic random access memories, voltage control oscillators, phase-lock loops, operational amplifiers, and switching capacitors. Such on-chip capacitors can also be used to decouple digital and analog integrated circuits from the noise of the rest of the electrical system.
Heretofore, such capacitors have been fabricated by building parallel plate capacitor structures using two or more layers of metal in the integrated circuit. This type of structure has provided a high-capacitance, stable, predictable and low leakage on-chip capacitor. However, one shortcoming of this structure is that a large area of the chip is required. To reduce the required area, designers have stacked multiple layers of metal which are alternately connected to form the opposing electrical nodes of the capacitor.
The present invention provides for a highly improved capacitor structure, which takes advantage of shrinking semiconductor process geometries. With present day advanced processes, a capacitor structure with two to three times the capacitance of conventional parallel plate structures occupying the same area of a chip is attained.